1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM).
2. Description of the Background Art
Semiconductor memory devices are employed in main memory devices of computers. A DRAM is one type of the semiconductor memory devices. FIG. 7 is a block diagram showing one example of an overall structure of a conventional DRAM. The structure of the DRAM will now be described with reference to FIG. 7. As shown in the figure, the DRAM includes a memory cell array 1, a row decoder 3, a column decoder 5, a row address buffer 7, a column address buffer 9 and a sense amplifier 11.
The memory cell array 1 is formed of a large number of memory cells which are unit storage circuits. The row address buffer 7 and column address buffer 9 store a row address signal and a column address signal, respectively. Information of the memory cells for reading/writing are transmitted in the form of the row address signal and column address signal. The row decoder 3 is provided between the memory cell array 1 and the row address buffer 7. The row decoder 3 decodes the row address signal. Decoding the row address signal selects a specific word line 15.
The column decoder 5 is provided between the memory cell array 1 and the column address buffer 9. The column decoder 5 decodes the column address signal. Decoding the column address signal selects a specific bit line 17. Selecting the bit line and word line selects a specific memory cell.
The sense amplifier 11 is provided between the memory cell array 1 and the column decoder 5. The sense amplifier 11 amplifies a signal stored in the selected memory cell to read the amplified signal.
An operation of the DRAM will be briefly described with reference to FIG. 7. First, with a row address inputted, a specific word line is selected. This selection of the word line causes all memory cells connected to the selected word line to be coupled to the sense amplifier 11.
Next, with a column address inputted, a specific bit line is selected. This selection of the bit line causes one sense amplifier in the sense amplifier 11 to be coupled to an input/output (I/0) circuit. Reading or writing is carried out in accordance with an instruction of a control circuit.
FIG. 9 is a plan view of a memory cell portion. As shown in the figure, a word line 19a and another word line 19b are provided in parallel. A bit line 21a and another bit line 21b are provided in parallel. The word lines 19a and 19b and the bit lines 21a and 21b are crossing over each other. The bit line 21a comprises an extended portion 22a and a contact portion 22b. An active region 26 is provided beneath the bit line 21a. The active region 26 extends in the same direction as the bit line 21a. The word line 19a intersects the active region 26. The word line 19b intersects the active region 26. The active region 26 has one end electrically connected to a storage node 23a and the other end electrically connected to a storage node 23b. A storage node 23c is provided above an intersection between the word line 19a and bit line 21b . A storage node 23d is provided above an intersection between the word line 19b and bit line 21b.
A cell plate 25 is provided in regions other than the region between the storage nodes 23a and 23b. The cell plate 25 is provided above the storage nodes 23a, 23b, 23c and 23d. A contact hole 27 is provided in a region between the word lines 19a and 19b above the active region 26.
There is a case where the word lines 19a and 19b make contact with an upper layer interconnection. When the word lines 19a and 19b make contact with a portion located on the active region 26, the following problem occurs. When an interconnection connecting the word lines 19a and 19b and the upper layer interconnection is connected with the active region 26 as well as the word lines 19a and 19b, shorts occurs. Thus, as shown in FIG. 9, the position where the word lines 19a and 19b are in contact with the upper layer interconnection is portions other than on the active region 26.
FIG. 10 is a cross sectional view of the memory cell of FIG. 9 taken along the direction of the arrow X. Referring to the figure, field oxide films 33a and 33b are formed at opposite ends of a main surface of a silicon substrate 29. The field oxide films 33a and 33b become insulator films for isolation. n.sup.+ regions 31a, 31b, 31c are formed spaced apart from one another in the main surface of the silicon substrate 29 between the field oxide films 33a and 33b. The region between the n impurity regions 31a and 31b is a channel region 20a, while the region between the n.sup.+ regions 31b and 31c is a channel region 20b.
A gate oxide film 35a is formed on the main surface of the silicon substrate 29 between the n.sup.+ regions 31a and 31b. On the gate oxide film 35a is formed the word line 19a to be a gate electrode. A gate oxide film 35b is formed on the main surface of the silicon substrate 29 between the n.sup.+ regions 31b and 31c. On the gate oxide film 35b is formed the word line 19b to be a gate electrode.
An interlayer insulation film 37 is formed on the field oxide films 33a and 33b, on the n.sup.+ regions 31a, 31b and 31c and on the word lines 19a and 19b. A contact hole 36a is formed in the interlayer insulation film 37 on the n.sup.+ region 31a. The storage node 23a made of polysilicon is formed over the interlayer insulation film 37 on the n.sup.+ region 31a. The storage node 23a and the n.sup.+ region 31a are electrically connected by the polysilicon filled in the contact hole 36a. A thin silicon oxide film 39a is formed over the surface of the storage node 23a. The silicon oxide film 39a is to be a dielectric. On the silicon oxide film 39a is formed the cell plate 25 made of polysilicon. The storage node 23a, the thin silicon oxide film 39a and the cell plate 25 constitute a capacitor 40a.
A contact hole 36b is formed in the interlayer insulation film 37 on the n.sup.+ region 31c. The storage node 23b made of polysilicon is formed over the interlayer insulation film 37 on the n.sup.+ region 31c. The storage node 23b and n.sup.+ region 31c are electrically connected by the polysilicon filled in the contact hole 36b. A thin silicon oxide film 39b is formed over the storage node 23b. The silicon oxide film 39b is to be a dielectric. On the silicon oxide film 39b is formed the cell plate 25 made of polysilicon. The storage node 23b, the thin silicon oxide film 39b and the cell plate 25 constitute a capacitor 40b.
An interlayer insulation film 41 is formed on the cell plate 25 and on the interlayer insulation film 37. The contact hole 27 is formed in the interlayer insulation films 37 and 41 on the n.sup.+ region 31b. On the interlayer insulation film 41 is formed the bit line 21a made of aluminum. The bit line 21a comprises the extended portion 22a and the contact portion 22b. The contact portion 22b of the bit line 21a is electrically connected with the n.sup.+ region 31b. On the bit line 21a is formed an insulator film 42.
FIG. 11 is a cross sectional view of the memory cell of FIG. 9 taken along the direction of the arrow XI. Referring to FIG. 11, field oxide films 33c and 33d and the gate oxide film 35b are formed in the main surface of the silicon substrate 29. The gate oxide film 35b is between the field oxide films 33c and 33d. The word line 19b is formed on the field oxide films 33c and 33d and on the gate oxide film 35b. On the word line 19b is formed the interlayer insulation film 37. The storage node 23d is formed on the interlayer insulation film 37. A thin silicon oxide film 39d is formed on the storage node 23d and at the side of the storage node 23d. The silicon oxide film 39d is to be a dielectric. The cell plate 25 is formed on the silicon oxide film 39d and on the interlayer insulation film 37.
The interlayer insulation film 41 is formed on the cell plate 25. The bit lines 21a and 21b are formed spaced apart from each other on the interlayer insulation film 41. The insulator film 42 is formed over the interlayer insulation film 41 and on the bit lines 21a and 21b.
The DRAM allows a state that electrons are stored in the capacitor to be correspondent with "0" of a digital binary signal and allows a state that no electrons are stored in the capacitor to be correspondent with "1" of the digital binary signal.
A method of writing data into the capacitor will now be described with reference to FIG. 10. In writing "0"a positive voltage is first applied to the word line 19a so as to form a channel in the silicon substrate 29 between the n.sup.+ regions 31a and 31b. Then, a 0V voltage is applied to the bit line 21a to put the n.sup.+ region 31b in a 0 V state. The electrons are thereby supplied from the bit line 21a to the capacitor 40a. The voltage applied to the word line 19a is then released. The writing of "0" into the capacitor 40a is thus completed.
In writing "1" into the capacitor 40a, a positive voltage is first applied to the word line 19a so as to form a channel in the silicon substrate 29 between the n impurity regions 31a and 31b. A 5V voltage is then applied to the bit line 21a to put the n.sup.+ region 31b in a 5V state. The electrons are thereby drawn from the capacitor 40a to the bit line 21a. The voltage applied to the word line 19a is then released. The writing of "1" into the capacitor 40a is thus completed.
A method of reading data will now be described with reference to FIG. 10. A voltage is applied to the bit line 21a to make the bit line 21a have a predetermined potential Vp. This is called a precharge of the bit line 21a. After precharged, the bit line 21a is electrically separated from a power supply to be brought into a floating state.
Next, a positive voltage is applied to the word line 19a so as to form a channel in the silicon substrate 29 between the n.sup.+ regions 31a and 31b. The electrons stored in the capacitor 40a and those existing in the n.sup.+ impurity region 31b are thereby averaged. Consequently, when data of "0" is written in the capacitor 40a, the electrons stored in the capacitor 40a are expelled to the n.sup.+ region 31b, so that a potential on the bit line 21a is slightly lowered from Vp down to Vp'.
When data of "1" is written in the capacitor 40a, there are few electrons in the capacitor 40a, so that the potential Vp on the bit line 21a hardly varies. These voltage variations are amplified by the sense amplifier 11 shown in FIG. 7, so that the data of "0" or "1" is read out.
A floating capacitance of the bit line is approximately 10-20 times larger than a capacitance of the capacitor. Therefore, there is only a slight difference in signal voltage appearing on the bit line between upon reading "1" and "0". Thus, the conventional DRAM shown in FIGS. 9, 10 and 11 has such a problem as will be described below.
As shown in FIG. 11, only insulator films 41 and 42 are between the bit lines 21a and 21b. It is assumed that a voltage on the bit line 21b varies, for example, front: 0 V to 5V while the bit line 21a is reading data. It sometimes happens that because of the voltage variation on the bit line 21b, an electric field in a region between the bit lines 21a and 21b changes, and hence the voltage on the bit line 21a slightly varies. The variation in voltage on the bit line 21b causes the bit line 21a to transmit erroneous data (for example, not "0" but "1" or visa versa) to the sense amplifier. The erroneous data causes erroneous operation of the memory device.
A description will now be given on the fact that a voltage on a bit line influences voltages on adjacent bit lines, with reference to an equivalent circuit diagram and a waveform diagram of a memory cell. FIG. 8A is an equivalent circuit diagram of a memory cell. A memory cell 13 includes a set of a field effect transistor Q and a capacitor Cs. Bit lines B0 and B0. constitute one bit line. Bit lines B1 and B1 constitute one bit line. A word line is denoted with a symbol WL, and a sense amplifier is denoted with a symbol SA.
FIG. 8B is a waveform diagram of voltages on the bit lines B0, B0, B1 and B1. The voltage on the bit line B1, which should be shown by dotted lines, is actually shown by solid lines. This is because the voltage on the bit line B0 influences the voltage on the bit line B1. Since the voltage on the bit line B1 is shown by the solid lines, the voltage on the bit line B1 is also shown by solid lines. Accordingly, the bit line constituted by the bit lines B1 and B1 transmits erroneous data to the sense amplifier. A DRAM which serves to solve this problem is described below.
This DRAM is disclosed in IEDM (International Electron Devices Meeting) 88, pp. 596-599. FIG. 12 is a plan view of a memory cell of this DRAM. This memory cell is hereinafter called a buried-bit line type memory cell. Referring to FIG. 12, word lines 45a, 45b and 45c extend in parallel spacing apart from one another. Bit lines 47a and 47b extend perpendicularly to the direction of the extending word lines 45a, 45b and 45c. The bit lines 47a and 47b extend in parallel spaced apart from each other. An active region 43a extends obliquely from the word line 45a to the word line 45b. The active region 43a intersects the bit line 47a. A storage node 49a is electrically connected to one end of the active region 43a, which is on the word line 45a side. A storage node 49b is electrically connected to the other end of the active region 43a. An active region 43b extends obliquely from the word line 45c to an adjacent word line (not shown in FIG. 12). A storage node 49c is electrically connected to one end of the active region 43b, which is on the word line 45c side.
FIG. 13 is a cross sectional view of the buried-bit line type memory cell of FIG. 12 taken along the direction of the arrow XIII. As shown in FIG. 13, impurity regions 53a, 53b and 53c are formed spaced from one another near a main surface of a silicon substrate 51. A gate oxide film 55a is formed on the main surface of the silicon substrate 51 between the impurity regions 53a and 53b. The word line 45a is formed on the gate oxide film 55a. An insulator film 57a is formed on and at opposite sides of the word line 45a.
A gate oxide film 55b is formed on the main surface of the silicon substrate 51 between the impurity regions 53b and 53c. The word line 45b is formed on the gate oxide film 55b. An insulator film 57b is formed on and at opposite sides of the word line 45b. A portion of the silicon substrate 51 between the impurity regions 53a and 53b is to be a channel forming region 56a. A portion of the silicon substrate 51 between the impurity regions 53b and 53c is to be a channel forming region 56b. All of the impurity regions 53a, 53b and 53c and the channel forming regions 56a and 56b connected together form the active region 43a shown in FIG. 12.
The bit line 47a is formed between the word lines 45a and 45b. The bit line 47a is electrically connected to the impurity region 53b. An insulator film 59 is formed on and at opposite sides of the bit line 47a.
The storage node 49a is electrically connected to the impurity region 53a. The storage node 49a is in contact with the insulator films 57a and 59. On the storage node 49a is formed a thin silicon oxide film 61a to be a dielectric. The storage node 49b is electrically connected to the impurity region 53c. The storage node 49b is in contact with the insulator films 57b and 59. On the storage node 49b is formed a thin silicon oxide film 61b to be a dielectric. A cell plate 63 is formed on the silicon oxide films 61a and 61b. On the cell plate 63 is formed an insulator film 62. FIG. 14 is an exploded view of the memory cell shown in FIG. 12.
As shown in FIG. 13, the bit line 47a of the buried bit line type memory cell is electrostatically shielded by the storage nodes 49a and 49b and by the cell plate 63. Therefore, no voltage variation on the bit line 47a shown in FIG. 12 causes a voltage variation on the bit line 47b. That is, when a voltage on the bit line 47a shown in FIG. 13 varies, charges are absorbed in a capacitor formed of the bit line 47a and the storage nodes 49a and 49b and in a capacitor formed of the bit line 47a and the cell plate 63.
However, in the buried-bit line type memory cell shown in FIG. 13, the bit line 47a, the storage nodes 49a and 49b and the cell plate 63 are formed after the formation of the word lines 45a and 45b. Thus, it is understood that the word lines 45a and 45b are not made of aluminum but polysilicon. This is possible because the melting point of polysilicon (1414.degree. C.) is higher than that of aluminum (660.degree. C.). That is, if the word lines 45a and 45b are of polysilicon, the word lines 45a and 45b do not melt in the formation of the bit line 47a or the like.
However, the sheet resistance value of polysilicon is 10-30.OMEGA./.quadrature., while that of aluminum is 30 m.OMEGA./.quadrature.. Therefore, power consumption of this buried-bit line type memory cell which has the word lines 45a and 45b made of polysilicon is increased.